Embedded

What’s involved in simulation of a complex SoC FPGA like Versal ACAP?

AMD’s Versal adaptive compute acceleration platform (ACAP) is a system-on-chip (SoC) device architecture (see figure 1) includes three groups of engines – scalar, adaptable, and intelligent – plus ...
Yahoo Finance

MicroCloud Hologram Inc. Launches FPGA-Based High-Performance Surface Code Quantum Simulation Platform

SHENZHEN, China, April 15, 2026 (GLOBE NEWSWIRE)-- MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the "Company"), a technology service provider, launched a simulator that fully leverages the ...
Nasdaq

Lattice Diamond Software Tool Delivers New Enhancements for FPGA Design, Simulation, and Verification

HILLSBORO, Ore.--(BUSINESS WIRE)-- Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced availability of the latest version of its popular FPGA design ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Electronic Design

Mixed-Language Simulator Serves FPGA Designers

In the Active-HDL Designer Edition, a low-cost mixed-language RTL simulator, designers gain a high-performance simulator for designs targeted at FPGAs. Basically, FPGA designers have been forced to ...
EDN

FPGA simulation kit aids PCB layout

The free Virtex-5 FPGA Simulation Kit is for use with the CR-5000 Lightning high-speed design solution and provides a set of topology templates and in-context HTML documentation for simulation of ...
Semiconductor Engineering

HDL Simulation Acceleration Solution For Microchip FPGA Designs

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
EDN

Aldec® Delivers $1,995 Mixed Language Simulator to FPGA Market

Active-HDL Designer Edition is available today and supports Windows 32/XP/Vista operating systems. The product is offered as a one year time based license and available as either a node locked ($1,995 ...