IEEE

Implementation and Extension of Bit Manipulation Instruction on RISC-V Architecture using FPGA

Abstract: The inclusion of Bit Manipulation Instructions (BMIs) has become more and more important as embedded systems continue to demand optimum performance together with a good energy economy.
GitHub

Generative Representational Instruction Tuning

GritLM-7B 7B parameter model that uses bidirectional attention for embedding and causal attention for generation. It is finetuned from Mistral-7B 66.8 55.5 GritLM-8x7B 8x7B parameter model that uses ...
IEEE

Design and Implementation of 32-Bit MIPS-Based Softcore Processor with Enhanced Instruction Set on FPGA

Abstract: In this paper, the 32-bit MIPS HDL processor has been devised to serve the purpose of running Symmetric and Overloaded Instruction Set (SOMA) on an FPGA. The SOMA architecture is unique in ...